convert std_logic_vector to integer in Quartus

[EDA_hg81]

std_logic_vector to integer

I am using Altera Quartus II.

Please let me know which function can convert std_logic_vector to integer.

Thanks.

 

[FvM]

convert std_logic_vector to integer

Under ieee.std_logic_arith, it's:

int_signal1  <= conv_integer(UNSIGNED(slv_signal1));
int_signal2  <= conv_integer(SIGNED(slv_signal2));

Under numeric_std library, the conversion should look similar.

 

[sval]

integer to std_logic_vector

use ieee.numeric_std.all;

...<= to_integer(unsigned(....));
...<= to_integer(signed(....));