Convert Real Number to Standard Logic Vector with VHDL

[jose2]

standard logic vector

How convert Real Number to Standard Logic Vector with VHDL?

 

[FvM]

vhdl+convert from signed to std

Rather far from a clear question. I guess, you want the std_logic_vector to represent a number. But you have to specify the number format, e.g. signed or unsigned, fractional or integer, possibly a float format?

In synthesizable VHDL, real type can exist only as a constant or a variable for compile time calculation. Is that, what you intend?

 

[jose2]

vhdl convert time to integer

First Answer:

I guess, you want the std_logic_vector to represent a number. But you have to specify the number format, e.g. signed or unsigned, fractional or integer, possibly a float format?

In synthesizable VHDL, real type can exist only as a constant or a variable for compile time calculation. Is that, what you intend?

My answers and comments;

The format will be signed and float number (floating point). In other words, I will like to know how convert STD_LOGIC_VECTOR to SIGNED FLOAT NUMBER.


Thanks in advance!!

 

[FvM]

vhdl real to unsigned

In other words, you want to know, how real numbers can be represented by std_logic_vector using a floating point format?

IEEE 754 defines the float formats, that are mostly used. These standard formats are known as single and double in C language implementation. Float IP provided by programmable logic vendors uses either this standard formats or custom specific formats with parameterizable mantissa and exponent width.

The VHDL float package can be used as a starting point
**broken link removed**