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Conversion of octal to decimal

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sugubai

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need help frds.. want some idea or verilog code for conversion of octal to decimal... the octal number is (106) base 8 and its binary number are (001 000 110) base 2 all we know..but how to write the verilog code for it.. i tried but it has shown some error... the code is

Code Verilog - [expand]
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module hgf(oct,bin);
input [0:2]oct;
output [7:0]bin;
reg[0:2]n;
reg [7:0]k;
integer i,d;
always@(*)
begin
n = oct;
for(i=0;n<=1;i=i+1)
begin
d=d+(n%10)* 8**i;
n=n/10;
end
i=1;
while(d!=0)
begin
k = k+(d%2)*i;
d=d/2;
i=i*10;
end
 
end
assign bin=k;
endmodule



pls anybody know help me frds
 
Last edited by a moderator:

Re: conversion of octal to decimal

Your title says convert octal to decimal. Your post says octal to decimal. But your output value is binary. Which is it? It LOOKS like you're trying to do octal to binary.
 
Re: conversion of octal to decimal

I think what they want (based on the poor description given) is a octal to a decimal value that is in binary.

The code as written is not synthesizable. A while loop is not normally synthesizable.

You are writing your code as if Verilog is C code. Verilog is a Hardware Description Language. You are not writing your code with any thought that this needs to be synthesized to a combonational circuit.

This is obviously wrong:
Code:
input [0:2]oct;
This does not represent the digits 1, 0, and 6. You are just declaring a 3-bit bus with reversed indices (which can confuse anyone looking at your code, basically you shouldn't do this).

An octal bus needs three 3-bit values to hold it, therefore the declaration should have been:
Code:
input [8:0] oct; // three 3-bit packed values
The thing is octal is easily translated to binary by doing the following:
Code:
assign bin[8:0] = oct[8:0];

your octal digits are oct[8:6]==3'b001, oct[5:3]==3'b000, and oct[2:0]==3'b110.

The only difference between binary, octal, and hex values is how may bits you group together. binary: 1-bit, octal: 3-bits, hex: 4-bits.

If you meant you wanted BCD (binary coded decimal) then you have to do an actual conversion, which there is a lot of code around that does this. https://en.wikipedia.org/wiki/Double_dabble
 
Re: conversion of octal to decimal

Sorry, I confused. it is a binary number.
 
Last edited by a moderator:

Re: conversion of octal to decimal

Sorry, I confused. it is a binary number.

As pointed out, Binary, Octal and Hexadecimal are all the same thing, grouped in different ways. So can you be clearer about what you're trying to do?
 

actually i need to convert octal number to binary using verilog..can anyone provide me the code for this conversion.

Thanks in advance.
 

its octal number multiplication.. tha is (106)base8*(6)base8=(644)8 it is normal octal multiplication we all know... i need the verilog code for this step step which means that that octal number will be converted into binary and then bcd and we multiply the one by one bit that is

bcd value are (0001 0000 0110)*(0110) right in this first step then we get output in bcd number that bcd will be convert binery and then octal value of (644)
 

You didn't yet manage to explain the format of your octal number input. The module port definition input [0:2]oct; has been already revealed as erroneous. What is the actual input coding?

Either you already have binary coded octal, then no conversion is needed at all, just concatenate the digit bits. Or you have something like an ASCII coded octal string, e.g. read from a terminal. Please clarify.

- - - Updated - - -

Why not answer the previous question with a clear input port definition?

BCD can be read as binary coded octal in this case, and due to the power of 2 two base, doesn't need conversion, just bit concatenation as said. Verilog understands * operator for the multiply.
 

its octal number multiplication.. tha is (106)base8*(6)base8=(644)8 it is normal octal multiplication we all know... i need the verilog code for this step step which means that that octal number will be converted into binary and then bcd and we multiply the one by one bit that is

bcd value are (0001 0000 0110)*(0110) right in this first step then we get output in bcd number that bcd will be convert binery and then octal value of (644)

This has to be some silly artificial school assignment. There is no reason to convert to bcd to multiply octal values concatenate and multiply.

(001 000 110)*(110)=(110)(100)(100) the binary answer, which you convert to bcd with the previous algorithm.
 

sir please help me sir...if u know how to write the code of verilog for this please provide me
 

sir please help me sir...if u know how to write the code of verilog for this please provide me

Yeah, I know how to write code to do anything that is well defined, but that is not the function of this forum. You need to make an effort to learn and take advice from other forum members and explain your problem in detail with examples/drawings/etc and present what you have written/attempted/etc and the errors/warnings/simulation_problems/etc. you are getting.

Asking for code is NOT the way to get help.
 
Asking for help via the PM system is also NOT the way to get help.

First of all read this. As you don't seem to understand how to ask a question. Furthermore respond to questions and comments about your code that are submitted by other members. Especially mine as to why you are using [0:2] as your octal input, which is still the same in the PM code you sent (identical to you original code), after I already told you that was not going to work.

Until you show you are making an effort to fix problems in your code, explain in detail exactly what you are trying to accomplish, and respond to questions/comments on your code. I will submit no further replies.
 
thk u sir for ur advice.. i tried my best.. i convert that octal number into binary and then bcd... next step is multiplication that is (0001 0000 0110)*(0110) in this 0110*0110 the code is

Code Verilog - [expand]
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module ily(
    input [11:0] a,
    input [3:0] b,
    output [7:0] p );
             wire [3:0]pp0,pp1,pp2,pp3;
             wire c1,c2,c3,c4,c5,c6,c7,c8;
             wire s1,s2,s3,s4,s5,s6;
bb t1(bcd,a);
bp t2(bc,b);
 
assign pp0=a[0]*b[3:0];
assign pp1=a[1]*b[3:0];
assign pp2=a[2]*b[3:0];
assign pp3=a[3]*b[3:0];
assign p[0]=pp0[0];
 
alf w1(pp0[1],pp1[0],p[1],c1);
ull w2(c1,pp0[2],pp1[1],s1,c2);
alf w3(s1,pp2[0],p[2],c3);
ull w4(c2,c3,pp0[3],s2,c4);
ull w5(s2,pp1[2],pp2[1],s3,c5);
alf e6(s3,pp3[0],p[3],c6);
ull w7(c4,c5,c6,s4,c7);
ull w8(s4,pp1[3],pp2[2],s5,c8);
alf w9(s5,pp3[1],p[4],c9);
ull w10(c7,c8,c9,s6,c10);
ull w11(s6,pp2[3],pp3[2],p[5],c11);
ull w12(c10,c11,pp3[3],p[6],p[7]);
endmodule



the error is

Error: Net "a[0]~11", which fans out to "Mult0", cannot be assigned more than one value
Error: Net is fed by "bb:t1|bcd[0]"
Error: Net is fed by "a[0]"
Error: Net "b[3]~0", which fans out to "Mult0", cannot be assigned more than one value
Error: Net is fed by "bp:t2|bc[3]"
Error: Net is fed by "b[3]"
Error: Net "b[2]~1", which fans out to "Mult0", cannot be assigned more than one value
Error: Net is fed by "bp:t2|bc[2]"
Error: Net is fed by "b[2]"
Error: Net "b[1]~2", which fans out to "Mult0", cannot be assigned more than one value
Error: Net is fed by "bp:t2|bc[1]"
Error: Net is fed by "b[1]"
Error: Net "b[0]~3", which fans out to "Mult0", cannot be assigned more than one value
Error: Net is fed by "bp:t2|bc[0]"
Error: Net is fed by "b[0]"
Error: Quartus II Analysis & Synthesis was unsuccessful. 15 errors, 48 warnings
Error: Peak virtual memory: 220 megabytes
Error: Processing ended: Tue Feb 06 00:44:33 2018
Error: Elapsed time: 00:00:02
Error: Total CPU time (on all processors): 00:00:02
 
Last edited by a moderator:

Sigh,.....

There are 10 types of people in the world: Those who understand binary, and those who don't.

Better learn how to use binary numbers:
https://www.youtube.com/watch?v=biqp0HjJmfk
https://ryanstutorials.net/binary-tutorial/

You might need a refresher in digital logic:
https://www.renesas.com/en-us/support/technical-resources/engineer-school/digital-circuits-01-and-circuit-or-circuit-not-circuit.html

Also I think you need to learn the basics of Verilog:

https://www.asic-world.com/verilog/veritut.html

Personally I learned Verilog by reading the book "The Verilog Hardware Description Language" by Thomas and Moory (it may have been the only Verilog book written at the time) and the updates to the language using the LRM in 2001. Of course that was easy to do as I already had a firm grasp of both binary numbers and digital logic design.

you could write the following simply as:

Code Verilog - [expand]
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// this...
assign pp0=a[0]*b[3:0];
// means this (without the multiplying):
assign pp0 = a[0] ? b[3:0] : 4'b0;
// with all the bit widths explicitly called out
assign pp0[3:0] = (a[0] == 1'b0) ? b[3:0] : 4'b0000;


Honestly I don't understand why you would want to do all the multiplications using muxes (if that is even what you are attempting). I suspect you don't even know what the digital circuit is supposed to look like for your design. I make that claim based on the information that you presented about converting octal to binary to BCD and then attempting to multiply BCD numbers. Unless multiplying in BCD is an idiotic requirement given as part of your assignment, you don't have a clue how to architect a design to meet the actual requirements in the most efficient way possible (or at least not in a way that makes things even harder to implement).
 

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