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conversion filter from simulink to vhdl

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fasto2008

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Hi,

Because i have obtained with Malab simulink simulation the same signal ouput as in the input.
I need to design decimation filter in VHDl code for this simulink sigma-delta anlog to digital converter.
osr=64 = 16 * 4
Fs=10.24MHz
fb=80Khz
nb=8bits
here i design the decimation with two sinus cardinal "comb–filter" (decimation of 16) and one compensation FIR filter (decimation of 4).

So i need your help for conversion this filter from simulink to vhdl code.




Thanks for help
 
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