[SOLVED] connecting modules in verilog

[xpratx]

hi,

i have a design where there are more than 1 o/p. now i want to call that o/p in other module as input. what should i do?

 

[FvM]

Consult your favourite Verilog text book about module instantations.

 

[Bubs23]

Just write another module with different name and port lists.Are your ports bidirectional?

 

[xpratx]

Consult your favourite Verilog text book about module instantations.

sorry don't have a book studying through internet so if you could point to some source i'l be grateful.

i'll try to be more specific. so there are two modules, data from output of one module is to be sent to the input of other module.
i have couple of things in my mind about what to do.
firstly i thought that i'll call module.
eg: module a (x,y,z)
b M1 (c,x,d); //module
so should i use the same variable name as 'x' in eg. or can i do that i use different variable like 'w' and then put x=w.

i was also thinking of calling both modules in a third module and put x=w there.

other thing i was thinking of was calling both modules in a TB and assigning it but i guess this will only work in simulation and not sythesis.

so someone could explain with a small eg. how to proceed.

 

[lostinxlation]

Searching on google with "verilog instantiation" can give you an instant answer.

 

[xpratx]

now in instantiation i have got
input a;
wire a;
alway @
a=1;

now i am not able to assign value to a wire.
how to do it?