Compensation Design for a DC/DC buck.

[jstefanop]

So I have a 5v->1v power stage built around the LM27403 for powering an ASIC, and it works well for lower operating frequencies in the rang of 100-250mhz, but things get unstable around 300mhz. Im trying to figure out how the compensation design works for this buck and how tuning it can help with 1) transient response of the buck (which I'm suspecting is one problem when the ASIC operates at high frequencies), and lowering high frequency ringing noise during MOSFET on/off switch.

Some background, buck switches at 250khz with a 1.3uH inductor with 2.3mOhm DCR, and 400uF output caps with 2mOhm ESR.

I understand that increasing the crossover frequency will increase load transient performance, but at what cost? I also read that a properly designed zero and pole placement can help with attenuation of the high frequency noise (mine is at 83mhz @ 100mv).

Based on my values this is a Type III B compensator which says the second zero and first pole should be placed to get the maximum phase lead at the crossover frequency, and the first zero should be half the first zero, and that second pole placed at half the switching frequency.

Now the design tool for the LM27403 says that the first zero should be placed at the complex double pole frequency (Flc) which is 7khz for my setup, and the second zero at the Flc resonant frequency (which I'm not sure sure where that is exactly). Then the first pole at the ESR zero frequency of the output cap, and the second pole at half the switching frequency.

So im a little confused at which approach is "right" and which would have the best performance for my design needs of fast transient response and attenuating high frequency noise. Ive attached what my bode plot looks like when going with the first approach.

(where would the LC resonant frequency be on this plot?).

 

[Warpspeed]

This is becoming a growing problem trying to keep the power up to increasingly fast, low voltage, power hungry circuitry that prodce huge sudden load changes.

The problem with buck converters is that no matter how hard you try, for stability the PI control loop must always take several switching cycles to adjust to a new load condition.

The latest trend now is away from PI control loops, and towards direct hystertic control.

The idea is that a simple voltage comparator on the dc output switches the buck converter on and off directly, with some small amount of hysteresis.
There are many refinements possible, but that is basically it.

And it can respond to sudden load changes in one switching cycle.
It vastly improves both switching dynamics and stability.

Key words to search " hysteric switching regulator" and "emulated ripple mode".

 

[jstefanop]

This is becoming a growing problem trying to keep the power up to increasingly fast, low voltage, power hungry circuitry that prodce huge sudden load changes.

The problem with buck converters is that no matter how hard you try, for stability the PI control loop must always take several switching cycles to adjust to a new load condition.

The latest trend now is away from PI control loops, and towards direct hystertic control.

The idea is that a simple voltage comparator on the dc output switches the buck converter on and off directly, with some small amount of hysteresis.
There are many refinements possible, but that is basically it.

And it can respond to sudden load changes in one switching cycle.
It vastly improves both switching dynamics and stability.

Key words to search " hysteric switching regulator" and "emulated ripple mode".

Sadly I did not do my research before starting this project, so I'm stuck with this buck for now. So I have to work with what I got.

 

[Warpspeed]

Sadly I did not do my research before starting this project, so I'm stuck with this buck for now. So I have to work with what I got.

High frequency ringing noise sounds to me to be more of a decoupling problem than a fundamental dc regulator design problem.
I would be looking more towards the load, and board layout/parasitics.

 

[FlapJack]

jstefanop, how did you do the bode plot.

 

[jstefanop]

jstefanop, how did you do the bode plot.

I used TI's tool for designing the LM27403

 

[mtwieg]

So I have a 5v->1v power stage built around the LM27403 for powering an ASIC, and it works well for lower operating frequencies in the rang of 100-250mhz, but things get unstable around 300mhz.

You're talking about millihertz? Are you sure?

I understand that increasing the crossover frequency will increase load transient performance, but at what cost? I also read that a properly designed zero and pole placement can help with attenuation of the high frequency noise (mine is at 83mhz @ 100mv).

So im a little confused at which approach is "right" and which would have the best performance for my design needs of fast transient response and attenuating high frequency noise. Ive attached what my bode plot looks like when going with the first approach.

Higher crossover frequency will mean faster rise and fall times, but as fc increases your phase margin will tend to decrease, which causes overshoot to increase, and the settling time to stay roughly constant. You should carefully consider exactly what you want your converter to do. Perhaps design to minimize the peak output error due to a certain load transient.

(where would the LC resonant frequency be on this plot?).

Should be identical to the conjugate pole frequency.

 

[treez]

you are using voltage mode control or current mode....current mode may make it easier for fast transient response, also using dcm mode may make it easier for you to get fast transient response...otherwise just increase your output capacitor bank.
You have the ray ridley book (volume 1 control)?...this is good for what you want and he shows how you can measure xover etc

 

[Easy peasy]

Really you need to seek expert help from a power electronics design engineer who has experience with the same problem, it is always a little layout dependant, and often component dependant too, e.g. ESL in o/p caps...

 

[FlapJack]

jstefanop, either you need a total redesign as warpspeed recommended or you could try adding more bulk capacitance to your circuit very close to your asic. I have seen up to 100uF low esr ceramic capacitors recommended for power hungry chips.

 

[jstefanop]

jstefanop, either you need a total redesign as warpspeed recommended or you could try adding more bulk capacitance to your circuit very close to your asic. I have seen up to 100uF low esr ceramic capacitors recommended for power hungry chips.

Yea I'm adding a 470uF poly cap (and taking one out of the four 100uf ceramics out), and adding 8x10uF caps around the input pins of the ASIC.

Hopefully that will improve things.