common clock for two processors

[Sunayana Chakradhar]

Hello,

I have a quad core imx6 processor and a zynq 7020 processor. Can I use a common external clock oscillator for these two? Is it sensible to do so? I want to do this to achieve synchronization.

 

[KD494]

It's my understanding that this is why clock fanout buffers exist. Can't speak from experience of whether your idea would work or not but I believe its more important that the clocks have EXACTLY the same frequency than are slightly lagging or leading the other. This is what you'll get with the buffer, someone feel free to correct me.

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I think it might have something to do with the proper termination of the clock line, sending it to two processors wouldn't provide the correct termination.

 

[andre_luis]

The global timing analysis is what should dictate the need of a specific scheme for clocking these modules either with distinct phases, or the actual clock, I guess.

 

[ads-ee]

Hello,

I have a quad core imx6 processor and a zynq 7020 processor. Can I use a common external clock oscillator for these two? Is it sensible to do so? I want to do this to achieve synchronization.

Synchronize in what sense? Using the same oscillator (i.e. frequency locked) will result in that frequency being the same for both devices, but both of these devices will have PLLs that multiply the frequency the processor sees to something else. If one is multiplied up by 5 say and the other is multiplied by 3 you're not going to have syncrhonization between the processors. If you have a signal that is sampled by both processors that is on the oscillator frequency that signal won't be synchronous to each processor as it will have to be transferred to the processors internal clock (hence they are no longer considered synchronous).

So once again what to do you mean by synchronization?

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Update...

You can read this paper on termination recommendations for clock oscillators from SiTime.

Depending on the edge rate of the clock oscillator you plan to use you may have to be very careful about the layout of the board. Two ICs driven by the same clock oscillator will probably work if the oscillator has enough drive strength (assuming you follow the recommendations in that paper). If it doesn't you'll end up with a distorted clock that could look more like a sine wave than a square wave, which will significantly increase the amount of clock jitter seen by both devices (potentially resulting in a non-functional board).

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Another option would be to drive the FPGA with the clock oscillator, and generate copies of the clock on two pins and route those with identical trace lengths to both a second FPGA clock input and to the iMX6 (If you can wait for the FPGA to be configured).

 

[Sunayana Chakradhar]

I have a Intertial motion sensor, few GSMs and a wifi module connected to the FPGA. There is the same IMU connected to the imx6 and a ddr3dram, a flash memory too. I wanted both these processors to run at a common external clock but now i understand that this might not be feasible as both the processors in my set up have PLLs set by different divisio values (ex:*5 for fpga and *3 for imx). Its better that these proceessors work on the existing interna clock frequencies which is 33.33 MHz for zynq 7020 fpga and 32 kHz for imx6.

 

[andre_luis]

I wanted both these processors to run at a common external clock but now i understand that this might not be feasible as both the processors in my set up have PLLs set by different divisio values

I've been examining the original question, asking to myself how much is plausible to consider as a need the use of the same clock in different soft cores. As far as I imagine, both modules are likely to be placed physically in different regions of the chip, so that a proper interface would be suited to interconnect signals from/to them, otherwise this would tend to add several meta stability constraints in terms of timing analysis after placement, isn't right ?

 

[Sunayana Chakradhar]

Both the processors are placed on the same pcb. They are connected to different modules. We want to avoid timing errors in clocking both these processors.

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My set up will be something similar to the one shown in the link mentioned below except for few changes made in the design

https://linuxgizmos.com/linux-sbc-mixes-freescale-imx6-with-xilinx-kintex-7-fpga/

 

[lismwong]

This is a common and very important issue while designing a board with multiple devices such as fpga, dsp, and memories. It is not the only way but a common way to synchronize their clocks. Here is an article talking about clock sync of multiple devices and inside fpga using Xilinx DCM/MMCM,
http://www.valpont.com/use-dcm-and-mmcm-for-xilinx-fpga-clock-deskew/pst/

 

[kvingle]

Hi,

I hope I understood your question correctly. It will never be possible to achieve synchronization between these two processors by using same clock generator.
But I am curious why you need them to be synchronous ?

 

[KlausST]

Hi,

If the question is: using one or two clock oscillators (of the same frequency) on one PCB but for multiple devices (microcontrollers, FPGA, ADCs, DACs...)

Then my answer is: Use ONE.

***
Whats the alternative?
Using two equal XTAL oscillators each with 50MHz for example.

They will differ in frequency. This will cause interference. If this interference really causes problems depends on the application.

...
Example 1) If there is data communication from one processor to the other.. with independent oscillators you have an unknown relationship between data transfer egdes of both processors.
A clean solution is to double buffer (to avoid metastable states) the input signal and feed it via FIFO to the receiving processor.
With one single clock source, you get a known relationship of the transfer edges of both processors. It is easier to adjust read write edges of both processors.
Usually there is no need for double buffering and FIFO.

Example 2) (Maybe here not of relevance) One clock for microcontroller (or FPGA) and ADC control.
With one single clock source you don´t have the interferance problem. If the analog signal is influenced by the clock source, then most of it results in an offset in the converted digital data.
An offset is easy to compensate.
But interference results in unknown (alias) frequencies. It is about impossible to filter them. So they remain conversion as uncertainty or noise.
Imagine a 50.000 MHz clock and a 50.001 MHz clock. Expect interferance with a frequency of 1kHz. Both clocks will vary with temperature and time and so does the interference frequency.

Klaus

 

[andre_luis]

It will never be possible to achieve synchronization between these two processors by using same clock generator

A priori there is no impediment to both CPUs operate with clocks becoming from the same oscillator, so the question apparently was answered. A further question which arose: how to get the synchronization to the phase of both.