guru hegde
Newbie level 2
Hi,
I have a group of incoming signals with different bit width belonging
to single transaction. I have to store all these inside FIFO or buffer
and forward all these to different block.I am coding in verilog. Is
there any way to do this without creating individual queue for each
signal.
Do verilog has something similar to structure in C so my problem can
be solved??
I have a group of incoming signals with different bit width belonging
to single transaction. I have to store all these inside FIFO or buffer
and forward all these to different block.I am coding in verilog. Is
there any way to do this without creating individual queue for each
signal.
Do verilog has something similar to structure in C so my problem can
be solved??