Code COverage and Regression Test Usage

[melonpy]

cadence cmview

For soc verification, the most important thing of RTL simulation is code coverage. We must guarantee that ourRTL verification acquires higher code coverage.

 

[andromeda]

Using of Code Coverage is very small part of Verification Process.
Those tool could help to find some holes untested in verification, but high Code Coverage (let say >90% for Line/Statement Coverage) don't mean anything. You could have 100% Statement Coverage and <50% of verified design functions. Or you could have 100% of verified design functions with 70% Statement Coverage (if your codding style is bad and to conservative).
All new simulator platforms and verification tools (like Vericity Specman) are built around Functional Coverage concept. Fuctional Coverage are quantitive measure which part of Verification Plan is achieved. New tools usually colect Fuctional Coverage information in post-processing, analyze them, and even (like Test Profiler in Specman) could help to create minimum Regression which cover maximum Functional Coverage.
Disadvantage of Functional Coverage is that, in contrary to Code Coverage which could be automatically collected, verification engineer must specify Functional Coverage items according Verification Plan, and it is more art then routine engineer job.

 

[lemon]

I also think function converage is more important,but code coverage can tell you whether there is redundance in your design.

 

[farmerwang]

high code coverage is mandatory; use functiona coverage to show if all your interested scenerio have been covered, however, this definitely included some coding/scripting

 

[zyphor]

It is a must to achieve high code coverage, but how to evaluate is a complicated question. It seems that a lot of eda software comparny want to give the answer to this question, such as TransEDA, Specman.

 

[flypig]

For The function coverage, the architecture prototype must be buit. It is rather difficuit. Maybe we have to get answers from tools such as openvera, Systemverilog?

 

[yeewang]

In short, function coverage depends on an experienced verification leader/team equipped with various EDAs including code coverage tools.

 

[joc_06]

The gui that is referred to in the first pdf - what is this? I have never seen this before. How do i invoke it ?
I have cmView but ive never seen this one.

thank you

 

[kinysh]

How do we compare these tools:
tranEDA
VS
Specman
VS
modelsim6.0 (assertion based)


My requirement is only internal state-machine coverage check.
which one is good?
Please help.

 

[funzero]

CAdence LDV51 support assertion either .

 

[spauls]

Code coverage is just a parameter to get confidence in verification ,
however try to get maximum expression coverage.

 

[sansprint]

hi:who used openvera?Can you tell me something about it ?I had studied it for a month,but i really don't know how to write a programe,can you tell how to write ?Thank you very much!:|

 

[jjww110]

Code coverage measures the elements of the code that havebeen exercised during testing. Code coverage includes statement, branches, condition, path, and data coverage. Tools with code coverage capabilities are available.

 

[Thomson]

Hello, the following attachment is the verification methodolgy manual 3rd, and may help to determine the extent to which your code coverage shall achieve.

as for Functional coverage, i think, you shall refer to the current topcis about assertion-based verification, coverage-driven verification, constrainte-random verification and testbench automation. Also, you may read SystemVerilog/SystemC/PSL for a reference.