clock mux to eliminate glitches in input signals which are not clocks

[fragnen]

Can a clock mux remove glitches if we need to connect the inputs of the clock mux with signals which are not clocks but these signals can produce glitches?

 

[kaushikrvs]

Clock mux in general makes the output glitch free. When both the clocks are low and the select signal is toggled; it switches output. If it works for clock; it should work for other signals as well.

 

[FvM]

The glitch-free feature depends on synchronisation of the mux control signal to the clock input. In a synchronous logic design, other signals than clocks are sampled at clock edges and don't need to be glitch-free outside the setup- and hold window.

In other words, it's almost unclear what you want to achieve. What do you exactly mean with " these signals can produce glitches"?

--- Updated Jan 22, 2021 ---

Clock mux in general makes the output glitch free.

Not quite right. Clock muxes allow glitch free clock switching. If the input clock itself has glitches, you are lost.

--- Updated Jan 22, 2021 ---

Referring to the thread title "eliminate glitches in input signals".

A clock mux does never eliminate gliches in input signal, neither for clocks nor other signals.

 

[fragnen]

The glitch-free feature depends on synchronisation of the mux control signal to the clock input. In a synchronous logic design, other signals than clocks are sampled at clock edges and don't need to be glitch-free outside the setup- and hold window.

In other words, it's almost unclear what you want to achieve. What do you exactly mean with " these signals can produce glitches"?

--- Updated Jan 22, 2021 ---

Not quite right. Clock muxes allow glitch free clock switching. If the input clock itself has glitches, you are lost.

--- Updated Jan 22, 2021 ---

Referring to the thread title "eliminate glitches in input signals".

A clock mux does never eliminate gliches in input signal, neither for clocks nor other signals.

There were clock muxes found in design with input signals which are not clocks. The signal which are input to these clock muxes can produce glitches. It is not understood the reason for presence of clock muxes instead of normal muxes in the design. Hence this thread is started. Why normal muxes are not used here and clock muxes are used?

Is clock mux found in library is same as glitch free clock mux? What are the differences between a clock mux found in library and a glitch free clock mux if clock mux found in library is not same as glitch free clock mux?

 

[ads-ee]

From what I've seen with clock muxing they do something like the ascii diagrams below.

         _____       _____       _____       ___
clk1  __|     |_____|     |_____|     |_____|   
         ___     ___     ___     ___     ___    
clk0  __|   |___|   |___|   |___|   |___|   |___
                   _____________________________
mux   ____________|                             
         ___     _   _____       _____       ___
clkm  __|   |___| |_|     |_____|     |_____|   
                 ^ mux glitch                   
         ___     ___             _____       ___
clkg  __|   |___|   |___________|     |_____|   
                       ^ clock out disabled

The mux control would cause the clkm to be produced as the clock immediately switches from clk0 to clk1. This results in a glitch.

The clock muxes I've seen will not switch the clock until it sees the edges of the clock and shuts off the mux output until an edge is seen on the clock being switched to resulting is something similar to the clkg output. In this example the clock being switched from (clk0) isn't switched away from until the clock pulse is 0 and the output doesn't immediately output clk1 until the next clock edge.

This is a simplified version of what a number of clock muxes I've seen are meant to do, they don't filter glitches they just avoid producing glitches on the clock switch over.

--- Updated Jan 22, 2021 ---

Whoever used a clock mux to "filter" glitches doesn't know what they were doing.

 

[fragnen]

Is it worthful to use clock mux when two separate resets need to be switched with test mode signal as the selection lines of the mux?

Is the clock mux provided by foundry same as glitch free clock mux?

 

[fragnen]

Can a clock mux that is provided by foundry in their libraries can filter glitches?