satishbabub
Newbie level 4
hello ,
i was trying to implement a clock multiplier by introducing a delay to one of the inputs to the xor gate here is my code
module clkmul( clk,A,B,C);
input clk;
output A,B,C;
reg A;
always
begin
A <= #2 ~clk ;
end
assign B = #1 clk ; //v9
assign C = A ^ B; // c is ouput clock
endmodule
will this logic work to multiply the clock period by 2
when i try to simulate this in modelsim i get an error saying "clkmul.v(9): near "#": syntax error, unexpected '#' "
can some one help me to sort out this ?
thanks
i was trying to implement a clock multiplier by introducing a delay to one of the inputs to the xor gate here is my code
module clkmul( clk,A,B,C);
input clk;
output A,B,C;
reg A;
always
begin
A <= #2 ~clk ;
end
assign B = #1 clk ; //v9
assign C = A ^ B; // c is ouput clock
endmodule
will this logic work to multiply the clock period by 2
when i try to simulate this in modelsim i get an error saying "clkmul.v(9): near "#": syntax error, unexpected '#' "
can some one help me to sort out this ?
thanks