clock multiplexer problem - help needed

[bigdog]

clock multiplexer

Hello,

I have two input clocks, CLKA and CLKB.
They go to a multiplexer directly from input port then generate a new clock CLK_SYS as the system clock of the whole circuit, but the select signal of the clock multiplexer comes from the CLK_SYS domain and its value is not a constant.
So, how should I define the clocks of this circuit?

Note: I use Synopsys design complier.

Thanks!

 

[rsqf]

Re: clock multiplexer

Hello,

I have two input clocks, CLKA and CLKB.
They go to a multiplexer directly from input port then generate a new clock CLK_SYS as the system clock of the whole circuit, but the select signal of the clock multiplexer comes from the CLK_SYS domain and its value is not a constant.
So, how should I define the clocks of this circuit?

Note: I use Synopsys design complier.

Thanks!

You could use the max frequency(in your design) clock to synthesis.

 

[bigdog]

Re: clock multiplexer

If I do so, how do I to do the timing analysis with PT, should I set case analysis since I have a multiplexer on the clock path?

 

[rsqf]

Re: clock multiplexer

If I do so, how do I to do the timing analysis with PT, should I set case analysis since I have a multiplexer on the clock path?

Yep, you could use the case analysis for safety

 

[bigdog]

clock multiplexer

Ok, thanks, I'll try that.

 

[oak_tree]

clock multiplexer

I don't think you need to. STA tools know to analyze both clocks. You'll get 2 paths.

 

[shitansh]

Re: clock multiplexer

Hello,

I have two input clocks, CLKA and CLKB.
They go to a multiplexer directly from input port then generate a new clock CLK_SYS as the system clock of the whole circuit, but the select signal of the clock multiplexer comes from the CLK_SYS domain and its value is not a constant.
So, how should I define the clocks of this circuit?

Note: I use Synopsys design complier.

Thanks!

Hi,

For this you have to use No-Glitch mux to switch clock attached file is application of clock multiplexer.


Also verilog file code of No-Glitch Mux is available from
**broken link removed**

I have did this before long time and i also used Synopsys design complier.

HTH
--
Shitansh Vaghela

 

[Jennis]

Hi Shitansh,

I know it is very old thread, But I need some help on this as you tested on DC.

I am using the same code which you mentioned for my design. I am not able to perform STA properly. I want to do power analysis for each clock and at the same time want to check how many registers clocked during case_analysis, so I am using the set_case_analysis but it is not working, means if I set select pin as 1 or 0 in both the case both the clocks are going to all registers. Have you experienced this issues, do I need to set any other constraints please let me know.

Anybody who knows anything about this, then please give some suggestion.

Thanks for reading this post.