clock input PAD has large delay time.

[cosmosd]

hi, my clock(HCLK_PAD) of desgin is input from a input PAD(PISW), when I reprot_timing -delay max, there are some violation path that the clock PAD contribute the most delay time, follow is one violation path:

(My clock period is 100ns ,but for the clock input PAD is 349.62 , so it's very strange, and when I simulation with this pad top, I got error results, so please help me! thx!)

****************************************
Report : timing
-path full
-delay max
-max_paths 1
-sort_by group
Design : PAD_TOP_NEW
Version: X-2005.09
Date : Fri Mar 12 22:40:24 2010
****************************************

# A fanout number of 1000 was used for high fanout net computations.

Operating Conditions: slow Library: slow
Wire Load Model Mode: top

Startpoint: HCLK_PAD (clock source 'HCLK_PAD')
Endpoint: uMulti_IO_NEW_USOC_TOP_uallslaves_uwrapper_fft_u_alu_urami
(rising edge-triggered flip-flop clocked by HCLK_PAD)
Path Group: HCLK_PAD
Path Type: max

Des/Clust/Port Wire Load Model Library
------------------------------------------------
PAD_TOP_NEW ForQA slow

Point Incr Path
--------------------------------------------------------------------------
clock HCLK_PAD (rise edge) 0.00 0.00
HCLK_PAD (in) 0.00 0.00 r
uHCLK_PAD/C (PISW) 349.62 # 349.62 r
uMulti_IO_NEW_USOC_TOP_uallslaves_uwrapper_fft_u_alu_urami/CLKA (rami)
0.00 # 349.62 r
data arrival time 349.62

clock HCLK_PAD (rise edge) 100.00 100.00
clock network delay (ideal) 15.00 115.00
clock uncertainty -0.50 114.50
uMulti_IO_NEW_USOC_TOP_uallslaves_uwrapper_fft_u_alu_urami/CLKB (rami)
0.00 114.50 r
library setup time -1.82 112.68
data required time 112.68
--------------------------------------------------------------------------
data required time 112.68
data arrival time -349.62
--------------------------------------------------------------------------
slack (VIOLATED) -236.94