Zorbas-E-
Newbie level 6
why clock gating using muxes
Hello all!
I'd like to ask you if you have noticed the same as I did when inserting clock gating in a design. I use Synopsys tools, i.e. Design Compiler-PowerCompiler for that.
So, what I observed is that when I apply clock gating the circuit area shrinks!
A little (1-2%), but is gets smaller.
Why does this happen? I mean, wouldnt you expect to grow a little by the introduction of the extra clock gating integrated cells?
thx for your time and reply in advance!
Hello all!
I'd like to ask you if you have noticed the same as I did when inserting clock gating in a design. I use Synopsys tools, i.e. Design Compiler-PowerCompiler for that.
So, what I observed is that when I apply clock gating the circuit area shrinks!
A little (1-2%), but is gets smaller.
Why does this happen? I mean, wouldnt you expect to grow a little by the introduction of the extra clock gating integrated cells?
thx for your time and reply in advance!