sagar_eda
Junior Member level 1
hi
i'm using RTL level clock gating in my design for reducing power consumption.
i'm taking everything ideal(setup time=0, hold time=0)
after inserting clock gating and after synthesis, i'm getting large hold time violations.
help me how to solve this
thank you
i'm using RTL level clock gating in my design for reducing power consumption.
i'm taking everything ideal(setup time=0, hold time=0)
after inserting clock gating and after synthesis, i'm getting large hold time violations.
help me how to solve this
thank you