clock detector for my senior project

[rakko]

clock detector

a question for those engineers out there. I am looking for a verilog digital circuit that outputs a 1 as long as clock is running and outputs a zero if the clock stops. anyone knows how to do this.

 

[echo47]

clock detection verilog

Remember that synthesized HDL has no concept of time. Do you have a second clock available? Or maybe some other hardware time-delay device? You can use one of those things to create a time window. During that window, you count the input clocks. If the count is zero, then the input clock is not running.

 

[AlexWan]

clock detection circuit verilog

Hi rakko,

Is there a clock enable signal of your design? Or use it with a input signal?

Good Luck

 

[quake]

clock detection circuit

a question for those engineers out there. I am looking for a verilog digital circuit that outputs a 1 as long as clock is running and outputs a zero if the clock stops. anyone knows how to do this.

Hi, my question is do you have any other clock than this? If not, can the stop behavior of the clock be detected? I don't believe it can, since any clock detector should work depending on this uique clock. I you have other clock sources, then
there exits a reference for detection, whatever clock cycles it takes for the other
clock to notice that the original clock stops. If there is a clock source with the same
frequency, you can add some regs to delay the origianl clock by several cycles, and check with the original one to see if there are any difference at any time.
Anyone have some sugestions?

 

[luancao]

clock detector

You should have another stable reference clock.

The clock detector works under the reference clock domain. And you should know the frequency range of the "clock" to be detected. If the frequency of the reference clock is much higher than the "clock" to be dectected, you could detected the changing from 0 to 1 or/and 1 to 0 within a time window. If the frequecy of the reference clock is lower. you could divide the detected "clock" by some value to make the new "clock" frequency at least 2 times lower than the reference clock, then detect the new "clock". The result is the same.

Added after 5 minutes:

What if you have only one clock, the detected clock?

XOR the toggled output from two DFF with inverted clock? ... or some tricks like that... Should also work...

Seldom will such situation appear in the real design.

 

[nand_gates]

clock detector vhdl code

If you have only single clock then you will have to use retriggerable
monoshot, keep time constant of retriggerable monoshot little greater than
the clock period of clock you want to detect!

If you have two clocks say sys_clk and clk_in. Then use following code!
Note here that according to the difference in sys_clk and clk_in frequencies
you need to tune the following code!

Hope this helps!

module clk_detect(/*AUTOARG*/
   // Outputs
   clk_ok, 
   // Inputs
   sys_clk, reset_n, clk_in
   );
   input sys_clk, reset_n, clk_in;
   output      clk_ok;

   reg [8:0]   count_clk_in;
   reg [7:0]   count_sys_clk;
   reg         cy_count_clk_in_r, cy_count_clk_in_rr;
  
   wire        reset_cnt = ~cy_count_clk_in_rr &  cy_count_clk_in_r;

   assign      clk_ok = ~count_sys_clk[7];

   always@(posedge clk_in or negedge reset_n) begin
      if (!reset_n)
        count_clk_in <= 0;
      else
        count_clk_in <= count_clk_in + 1'b1;
   end
   
   // double flop synchronizer for clk_in counter carry!
   always @(posedge sys_clk or negedge reset_n) begin
      if (!reset_n) begin
         cy_count_clk_in_r <= 1'b0;
         cy_count_clk_in_rr <= 1'b0;
      end else begin
         cy_count_clk_in_r <= count_clk_in[8];
         cy_count_clk_in_rr <= cy_count_clk_in_r;
      end
   end
// retriggerable monoshot!      
   always @(posedge sys_clk or negedge reset_n) begin
      if (!reset_n) begin
         count_sys_clk <= 0;
      end else begin
         if (reset_cnt)
           count_sys_clk <= 0;
         else if (!count_sys_clk[7]) 
           count_sys_clk <= count_sys_clk + 1'b1;
      end
   end 
endmodule // clk_detect

 

[pilmot]

simple clock-detection circuit -patent

I think u have a little problen in the beginng (right after reset).
In case after resert system clock is stabel but we don't have clk_in
count_sys_clk will count and there will be a time (256 sys clocks) which clk_ok will show '1' but clk_in is not ok.
In my simulation the ratio is sys_clk/clk_in = 50/1

 

[laglead]

vhdl code for retriggerable monoshot

clock enable signal maybe a choice

 

[tukken]

verilog clock detector

a reference clock is required