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Choosing Lead, Active and Trail timings

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vhn

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Hi,
I'm working on DSP TMS320F2812 from TI. I want to interface an external SRAM to it. I've chosen the external interface zone 7 to interface SRAM to DSP.
According to the datasheet the SRAM would take 10 ns for a write / read cycle. I'm running the DSP at 150 MHz clock (30 MHz * 5). So, each clock cycle would be around 7 ns.
Now, there are three timing registers in DSP, namely Lead, Active and Trail.

Can anyone tell me how should I choose the values for Lead, Active and Trail timing so that the SRAM communication will be successful.

Thanks,
vhn
 

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