Change in functioning of FSM

[Tapojyoti Mandal]

I am trying to implement a FSM but there are 3 different versions using which a FSM can be designed(It is mentioned in Xilinx XST guide).Each version uses different number of Process.

process1: process (clk,reset)
begin
    if (reset ='1') then
        state <=s1;
    elsif (clk='1' and clk'Event) then
        state <= next_state;
    end if;
end process process1;

process2 : process (state,x3)
begin
    case state is
        when s1 =>  (don't care)
        when s2 =>  if x2='1' then
                        next_state <= s1;
                    elsif x2='0' then
                        next_state <= s4;
                    end if;
        when s3 => (don't care)
        when s4 => (don't care)
    end case;
end process process2;

process3 : process (state)
begin
case state is
    when s1 => outp <= '11';
    when s2 => outp <= '01';
    when s3 => outp <= '10';
    when s4 => outp <= '00';
end case;
end process process3;

This is my FSM with three Process design.Now, let's say that 'x2' is supplied by a logic block which makes decisions on the negative edge transition of clock.
Present state of inputs/state/output:

    x2='1'    
    state=s2  
    outp='01'  
    next_state=s1

Now, at next negative edge, the logic block changes the inputs based on the 'outp' it received, as follows:

 x2='0'

As a result:
next_state changes to 's4',because 'x2' is present in sensitivity list of process2.
And in the next positive logic my FSM goes into 's4' state.

process (clk,reset)
begin
    if (reset ='1') then
        state <=s1;
        outp<='1';
    elsif (clk='1' and clk'event) then
        case state is
            when s1 => (don't care)
            when s2 =>  if x2='1' then
                                state <= s1;    
                                 outp <= '11';
                             elsif x2='0' then
                                 state <= s4;
                                 outp <= '00';
                        end if;
            when s3 => (don't care)
            when s4 => (don't care)
        end case;
    end if;
end process;

This is my FSM design with single Process
Let's assume the same input scenario:

    x2='1'   
    state=s2  
    next_state=s1  
    outp='11'

Now,Based on 'outp', at next negative edge, the logic block changes the inputs based on the 'outp' it received, as follows:

  x2='0'

But this time my FSM doesn't changes it's decision of state midway, and hence at next positive edge FSM goes into state 's1'

So, in two different implementations at the next positive edge my FSM goes into two different states.In 3-Process my 'FSM' goes into 's4' state while in single Process FSM goes into 's1' state.


In the three process version when 'x2' changes from 1 to 0 at -ve clock edge my FSM goes to state 's4' at next +ve clock edge. In single process version when 'x2' changes from 1 to 0 at -ve clock edge it causes no effect and my FSM goes into state 's1'. So, because of following 2 different versions of syntactical description of FSM causes my FSM to go into different states due to 'x2' as external change. But xilinx guide nowhere mentions that the functioning should change.

 

[TrickyDicky]

According to your code and what I tried to understand from your odd description, in both the examples the outp value will end up being "00", and both examples end up in the s4 state. It doesnt matter what the next_state is, because the state only changes on the positive edge of the clock. You get the same behaviour in the single process - so if x2 changes from 1 -> 0 between edges, both will end up in the s4 state.

This is a very poor example, and if you do have logic in two different clock domains (pos edge, and neg edge) then you are probably designing the whole system wrong, so Im guessing there are flaws in the real code and the design.

Also, why should Xilinx tell you the two produce changes? both your code examples are different. 3 process has unregistered outputs, the single process has registered outputs.

What you really want to do is take a step back and draw out the logic circuit before writing the code.

 

[FvM]

We can also start analysis from reset, in this case both designs are (possibly) stuck at s1. I really don't see what the example should be good for.