Chaining transistors - interdigitating the 3 PMOS

[umagne]

Chaining transistors

I'm trying to layout a current mirror and I have some doubts. It's a simple PMOS current mirror (2 transistor M5 and M7) that mirror the current on an additional PMOS (M9). the widths and lengths are:
W5=8um, L5=50um
W7=8um, L7=50um
W9=24um, L9=50um
1) it's useful according to you, for matching purposes, to interdigitate the 3 PMOS?
2) naming M9=C, W7=B, W5=A, it would be a good choice a pattern like
CACBC
CBCAC
(using finger of 4um)?
Thanks

 

[erikl]

Re: Chaining transistors

1) it's useful according to you, for matching purposes, to interdigitate the 3 PMOS?
2) naming M9=C, W7=B, W5=A, it would be a good choice a pattern like
CACBC
CBCAC
(using finger of 4um)?
Thanks

Why not? Yes, that's fine. Don't forget the side dummies. 1 finger is enough.

 

[Fom]

Chaining transistors

I'd prefer put the reference transistor A in the middle: CBACC or CCABC.

 

[walker5678]

Re: Chaining transistors

L=50u?

 

[umagne]

Re: Chaining transistors

L=50u?

yes L=50um. This mirror is embedded in a current reference and I found that the sensitivity to power supply variations lower using long channel for those transistors not diode-connected.
Do you think is a bad idea to use so long channel? Why?

Added after 2 minutes:

Why not? Yes, that's fine. Don't forget the side dummies. 1 finger is enough.

What do you mean with: "1 finger is enough"? C is divided in three part and A and B are only one finger.

 

[antonio_eda]

Chaining transistors

1 finger side dummy structure for better fabrication.