d123
Advanced Member level 5
Hi,
I do not understand the truth table for the CD54HC173 (High-Speed CMOS Logic Quad D-Type Flip-Flop, Three-State). At all.
What combinations are needed to get a high on Q0, Q1, Q2, Q3? Can you have multiple outputs asserted? What combination(s) for all outputs to be low on power-up?
To avoid the problem of a flip flop like the CD4013 or similar randomly asserting Q or !Q on power-up, but never having the option of neither output being high, would this IC be a suitable (if slightly pricy, ~ €4 each on AVNET) alternative?
Thanks.
I do not understand the truth table for the CD54HC173 (High-Speed CMOS Logic Quad D-Type Flip-Flop, Three-State). At all.
What combinations are needed to get a high on Q0, Q1, Q2, Q3? Can you have multiple outputs asserted? What combination(s) for all outputs to be low on power-up?
To avoid the problem of a flip flop like the CD4013 or similar randomly asserting Q or !Q on power-up, but never having the option of neither output being high, would this IC be a suitable (if slightly pricy, ~ €4 each on AVNET) alternative?
Thanks.