cascode for more gain

[zeldazzz]

if i stack three mos on top of each other instead of two, I can get higher ro and more gain. But, what prevents me from doing that except head room?

 

[jigisha]

i think area and powerdissipation may be....

 

[checkmate]

You've given the main answer. Headroom.
Headroom is so short that some modern processes cannot even afford cascodes.
The other reason why we seldom stack 3 cascodes (even if we had the headroom) is that stacking 2 cascodes already gives us a high enough impedance for most applications.

 

[dick_freebird]

Stacking two, the guard FET gate drive is often a "freebie"
(tie to Vdd, or a capacitively-stiffened divider, etc. - it has
only to stay put.

Stacking three, at least one of them may need a "live" gate
drive to ensure that none of the trio sees overstress voltage.

You can work this out with a pencil for max neg, max pos
cases and determine where the gates can sit to do the job
of blocking / apportioning voltage.

Your on resistance pretty much follows sum(L) and by the
time you hit So3 you might prefer to just be in last year's
process - 3*Ltoday ~ 2*Lyesterday - with similar net
working voltage but simpler topology and lower cost.

I've made So28 drivers in SOI, where you don't worry
about BVdb, BVgb. But these limits may also bind up the
practical stacking in JI technologies - though they are
sometimes not explicitly stated in the short-form design
rules.