hosseineslahi7
Junior Member level 1
Dear All,
I have designed a circuit in 22nm FDSOI technology which can offer
frequency modulation if a bias is applied on the back-gate of a NMOS
(HVTNFET model). In this layout, consequently, I should use deep NWELL
to separate global substrate and local substrate of that particular
transistor with body bias. Following this approach, I should draw an
NWELL ring around this Tr and connect it to Vdd otherwise the parasitic
diode between local pwell and deep NWELL cause the total power
consumption to increase incredibly.
My question is how I can have access to the nwell ring in schematic
view? I have created an NPLUS contact on top of nwell ring and introduce
a pin for it but I do not know how I should introduce such a pin in the
schematic. This pin is needed to connect nwell ring to a new bias voltage. In addition, although there is an extra pin in layout
compared to the schematic, LVS cannot realize this pin and is always clean.
I appreciate any assistance in this regard.
Cheers,
Hossein
I have designed a circuit in 22nm FDSOI technology which can offer
frequency modulation if a bias is applied on the back-gate of a NMOS
(HVTNFET model). In this layout, consequently, I should use deep NWELL
to separate global substrate and local substrate of that particular
transistor with body bias. Following this approach, I should draw an
NWELL ring around this Tr and connect it to Vdd otherwise the parasitic
diode between local pwell and deep NWELL cause the total power
consumption to increase incredibly.
My question is how I can have access to the nwell ring in schematic
view? I have created an NPLUS contact on top of nwell ring and introduce
a pin for it but I do not know how I should introduce such a pin in the
schematic. This pin is needed to connect nwell ring to a new bias voltage. In addition, although there is an extra pin in layout
compared to the schematic, LVS cannot realize this pin and is always clean.
I appreciate any assistance in this regard.
Cheers,
Hossein