Can this be synteshized: if (clkevent and clk=1) then ?

[pavanvkulkarni]

synthesis errors...

hai,
Just wanted to clarify whether the following statement can be synthesised:
if (clk'event and clk='1') then
.........

We are facing a few errors....
Also we were told not to use the code as above i.e., 'and' operation in the above 'if' statement apparently produces glictches... is that true??... and if so how do we circumvent the problem....

also we are facing a lot of synthesis issues.... so it would be helpful if u could suggest a one stop solution for all our synthesis problems....

We are actually (as part of our project) trying to implement the avionics standard transceiver ARINC-429 on the FPGA (Spartan 3)...So any help in this regard is also welcome

Thank you all in advance
-Pavan

 

[dcreddy1980]

Re: synthesis errors...

if (clk'event and clk='1') then statement is synthesizable....and the statement wont produce any glitch problems.

if u have any further issues...do post them here

Regards,
dcreddy1980