Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Sorry, but I did write for you: "check by ddt694", I (and we) can not scroll with your hand + mouse:-(((, but I do attach it yet_only for you(of course)
Good luck!
K.
module multi_7 (
input rst ,
input clki ,
output reg error ,
output clko
);
reg [2:0] cnt ;
reg h ;
reg l ;
always @(posedge clki)begin
if(rst==1'b1)begin
cnt<=6;
end else begin
cnt<=(cnt>=6)?0:cnt+1'b1;
end
end
always @(posedge clki)begin
if(rst==1'b1)begin
h<=1'b0;
end else begin
h<=
(cnt==6)?~h:h;
end
end
always @(negedge clki)begin
if(rst==1'b1)begin
l<=1'b0;
end else begin
l<=
(cnt==3)?~l:l;
end
end
always @(posedge clki)begin
if(rst==1'b1)begin
error<=1'b0;
end else begin
error<=(cnt==6)?(clko):error;
end
end
assign clko = h ^ l ;
endmodule
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
