can increasing overall frequency help in saving GATECOUNT?

[simplybharath]

hi all

can increasing the frequency improve with reducing the GATECOUNT of the design , iam a newbie , i dont know if it is a proven strategy , can anybody explain me how ?

thanks in advance

 

[eshwartt]

Re: can increasing overall frequency help in saving GATECOU

Hi Bharath,

Increasing overall frequency will not help in saving gatecount.
Gatecount depends on functionality of the IC, Frequency, technology..etc.

Regards,
Eshwar.

 

[simplybharath]

Re: can increasing overall frequency help in saving GATECOU

in your reply u have mentioned frequency ...


can you pls explain me in little detail how it can help ?

like increasing frequency means reducing the clock period which would require faster gates or more buffers to meet timing ? i dont see anyway that it can save some gates , will like to get a more elaborative explaination on this pls

thanks

 

[eshwartt]

Re: can increasing overall frequency help in saving GATECOU

Answer lies in your question....

As a standard GC is calculated on area occupied by a 2 input nand gate. Let's say it occupies 2 area units. Area units may be sqmm.
Suppose if a 100Mhz design occupies say area of 500 area units. GC is 500/2 i.e 250 gates. and if a same design is synthesized at 200Mhz, design occupies say area of 800 (due to faster gates and buffers) now GC is 800/2 i.e. 400 gates.

To realize Faster gates you need larger area cells, addition of buffers also increase area. that will sum upto ur increase in GC.

If I go to device level. To drive a cell faster you need greater drain current(Id). Id is dependent on Width of the transistor. As width increase, area increase. cells are made up of one or more transistors...As size of transistors increase, effective cell size increases that contribute to GC.

Regards,
Eshwar.

 

[simplybharath]

Re: can increasing overall frequency help in saving GATECOU

thank you for such a clear explanation