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ftian said:Can I use both rising edge and falling edge in the same design for one clock?
Thanks,
Jay
barkha said:For increase data throughput rates, use is
sometimes made of both the rising and the falling clock
edge for clocked elements. But it causes a number of
problems, in particular:
• An asymmetrical clock duty cycle can cause setup and
hold violations.
• It is difficult to determine critical signal paths.
• Test methodologies such as scan-path insertion are
difficult, as they rely on all flip-flops being activated on
the same clock edge. If scan insertion is required in a
circuit with double-edged clocking, multiplexers must be
inserted in the clock lines to change to single-edged
clocking in test mode.
It will be more safe to use 2 multiple clk with you source clk singnal .
ftian said:Can I use both rising edge and falling edge in the same design for one clock?
Thanks,
Jay