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Hmmm,
Yes if you are planning something like daisy Chaining or buffering clk in one FPGA and giving input to other.
If not, use one clk buffer before giving clk to FPGA. Say 1:4 clk buffer where you can connect clk to four different FPGAs.
Depends on the clock frequency and the wiring. Basically yes. Source side termination (a 20 to 50 ohm series resistor near the oscillator) for each clock trace would be reasonable to reduce reflections, that possibly cause ringing edges and double clocking.
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