Can function be used in Verilog RTL?

[lostin_eda]

could function be used in Verilog RTL?

 

[guzhal]

Re: function used in RTL

Register transfer level abstraction is used in hardware description languages (HDLs) like Verilog and VHDL to create high-level representations of a circuit. In VHDL functions can be used, as there is concept of subprograms which comprises of procedures and functions .
I am not sure about verilog

 

[lostin_eda]

Re: function used in RTL

Register transfer level abstraction is used in hardware description languages (HDLs) like Verilog and VHDL to create high-level representations of a circuit. In VHDL functions can be used, as there is concept of subprograms which comprises of procedures and functions .
I am not sure about verilog

Sometimes, ALWAYS could be used in stead of FUNCTION. This kind use of FUNCTION could be used in RTL?

 

[guzhal]

Re: function used in RTL

always is a function used in verilog not in VHDL

 

[avimit]

Re: function used in RTL

Yes, Functions can be freely used in VHDL/Verilog RTL.
Kr,
Avi
http://www.vlsiip.com

 

[heartfree]

function used in RTL

Yes, Function feature can be used in verilog as a combination logic implementation.

 

[optor]

Re: function used in RTL

could function be used in Verilog RTL?

Sure, but it is suggested that using function only in testbench.

 

[avimit]

Re: function used in RTL

hi optor
why would you say so. I use functions all over the RTL.
Kr,
Avi
http://www.vlsiip.com

 

[supercst]

Re: function used in RTL

could function be used in Verilog RTL?

Sure, but it is suggested that using function only in testbench.

maybe not suggested. only task can only be used in testbench. sometimes function will be convenient for some circuits.

almost all the systhesis tools support functions.

 

[beta0]

Re: function used in RTL

Yes, Function feature can be used in verilog as a combination logic implementation.

Right, Function are usually used for implementation some combination logic at RTL
level