Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

can dynamic dither use in single bit sigma-delta ADC?

Status
Not open for further replies.

carlyou

Member level 4
Member level 4
Joined
Dec 6, 2004
Messages
78
Helped
2
Reputation
4
Reaction score
2
Trophy points
1,288
Activity points
771
I want to design a five_order signle bit simga_delta ADC, I see the dnamic dither in the book, but it seems to use multi-bit DAC, can I use it in my design?
 

dither is used to suppress idle tone.
generally,high order modulator don't use dither due to its tone behavior.
So,i don't think fifth order,single stage delta-sigma modulator need to be dithed.
 

Well, 3x very much. I have another problem. why someone add additive zeros in the standard structure?
 

the zeros placed in the baseband(not in dc) can further suppress the
quantization noise energy(in baseband), which means we can get higher SNR.
It can be easily seen from the spectrum of 1bit output data stream.
 

    carlyou

    Points: 2
    Helpful Answer Positive Rating
Idle tones may appear in high-order modulators. The phenomenon should be checked in simulation or measurement.
 

but should I add dither to my design? Now, I have read books and papers for so long time, I have no idea with my disign, should I choose a simple model and begin my system analysis or continue to learn the knowledge ? PS: now I read the book "Delta-Sigma Data Converters: Theory, Design, and Simulation.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top