can anyone give some points about low voltage CMOS VCO?

[wildgoat]

i am busy with it now
can anyone give some suggetions about how to choose the architecture and the physical parameter of cmos fet?
bow!

 

[khouly]

u can begin the design by chosing one of -gm architectures of CMOS VCO , then try to estimate the resistance of the tank circuit , and then chose a suitable startup factor , and then begin to design the GM of the cross coupled pair to be the resistannce of the tanks * startup factor
alway the startup factor = 2 to 3

then u got the GM and begin to desing the circuit and see the current which will be feed to the oscilator

then try to optimize the rsult to get lower phase noise

 

[wildgoat]

u can begin the design by chosing one of -gm architectures of CMOS VCO , then try to estimate the resistance of the tank circuit , and then chose a suitable startup factor , and then begin to design the GM of the cross coupled pair to be the resistannce of the tanks * startup factor
alway the startup factor = 2 to 3

then u got the GM and begin to desing the circuit and see the current which will be feed to the oscilator

then try to optimize the rsult to get lower phase noise

you are the first man tell me such methods
but i am not familiar with them
can you give them in details or give some docoments?

 

[khouly]

try to search in
www.circuitsage.com
**broken link removed**

u will find many publications about VCO design there

 

[uncle_urfi]

Professor Paul Allen's website
+ https://users.ece.gatech.edu/~pallen/


Try to find his PLL-synthesizer course notes there. That's all you need.

 

[andy2000a]

try to search in
www.circuitsage.com
**broken link removed**

u will find many publications about VCO design there

thank you ...

by the way ..

have anyone know where can I find design course about GM_c filter ??

 

[khouly]

if u found it plz send the link

thanks