Cutey
Member level 2
i programmed the fllowing code it is crrect but get wrong result
the fllowing code is shif multiplying
please if any one can tell me it get wrong result?
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity MUL is
Port ( clk : in STD_LOGIC;
-- i:in integer:=1;
result : out STD_LOGIC_vector(15 downto 0);
m : in STD_LOGIC_vector(7 downto 0);
n : in STD_LOGIC_vector(7 downto 0);
start:in std_logic);
end MUL;
architecture Behavioral of MUL is
signal count:integer:= 0;
signal n1,m1:std_logic_vector(7 downto 0);
signal result1:std_logic_vector(15 downto 0);
begin
process(clk)
begin
m1<=m;
n1<=n;
--result<=result1;
if (rising_edge(clk))then
if( start = '1' )then
result<="0000000000000000";
count <=0;
else
if (count /= 8 )then
if (m1(0)='1')then
result<=result1+n;
end if ;
n1 <=n(6 downto 0) & '0';
m1 <='0'& m (7 downto 1);
count <=count+1;
end if ;
end if;
end if ;
end process ;
end Behavioral;
the fllowing code is shif multiplying
please if any one can tell me it get wrong result?
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity MUL is
Port ( clk : in STD_LOGIC;
-- i:in integer:=1;
result : out STD_LOGIC_vector(15 downto 0);
m : in STD_LOGIC_vector(7 downto 0);
n : in STD_LOGIC_vector(7 downto 0);
start:in std_logic);
end MUL;
architecture Behavioral of MUL is
signal count:integer:= 0;
signal n1,m1:std_logic_vector(7 downto 0);
signal result1:std_logic_vector(15 downto 0);
begin
process(clk)
begin
m1<=m;
n1<=n;
--result<=result1;
if (rising_edge(clk))then
if( start = '1' )then
result<="0000000000000000";
count <=0;
else
if (count /= 8 )then
if (m1(0)='1')then
result<=result1+n;
end if ;
n1 <=n(6 downto 0) & '0';
m1 <='0'& m (7 downto 1);
count <=count+1;
end if ;
end if;
end if ;
end process ;
end Behavioral;