Cadence Virtuoso Layout for Power MOSFET need help

[ajeya]

Hi,

I am new to IC layout. I am finding it confusing to make a Power MOSFET (NMOS) width 9.2mm width and length 1.6u. As per schematic simulation study.

This seems to big to be drawn like simple nmos of small Width(um)and Length (um)

Can some one point me to the right resource or give suggestion on how to draw this Power MOSFET.

Thanks.

 

[erikl]

e.g. 1000 fingers of 9.2µm width.

See View attachment CIC_Workshop_on_Full_Layout_Technology.pdf, slides 23..26 .

Don't use Waffle transistors

... if your PDK doesn't allow 45°
... your LVS extractor cannot extract such structures
... the exact W/L ratio is important.