Cadence Virtuoso for mixed-signal designs

[elec-eng]

Hi guys

I intend to use Cadence Virtuoso in mixed-signal Design

my question is about the digital part

how a digital block is inserted in the workspace

is it used as a block of vhdl or verilog file with I/O ports to connect with the analog parts

or inserted as a synthesized netlist generated for Synopsys DC or Cadence encounter

generally,how to connect the digital part with the other anakog parts


thanks all

 

[AdvaRes]

Hi guys

I intend to use Cadence Virtuoso in mixed-signal Design

my question is about the digital part

how a digital block is inserted in the workspace

is it used as a block of vhdl or verilog file with I/O ports to connect with the analog parts

or inserted as a synthesized netlist generated for Synopsys DC or Cadence encounter

generally,how to connect the digital part with the other anakog parts


thanks all

Hi,
I dont know if it is possible to do that with candece Virtuoso but I know that Synopsys Saber can do that.

 

[elec-eng]

Hi,
I dont know if it is possible to do that with candece Virtuoso but I know that Synopsys Saber can do that.

Virtuoso is a design tool for Analog and mixed-signals designs

Saber is a simulation tool

I speak about design entry

How to insert a digital block and connect it with the other analog parts

what is the type of the inserted block

is it a vhdl file

or a netlist generated by Synopsys DC or encounter

 

[AdvaRes]

Hi,
I dont know if it is possible to do that with candece Virtuoso but I know that Synopsys Saber can do that.

Virtuoso is a design tool for Analog and mixed-signals designs

Saber is a simulation tool

I speak about design entry

How to insert a digital block and connect it with the other analog parts

what is the type of the inserted block

is it a vhdl file

or a netlist generated by Synopsys DC or encounter

Yeah, I know that Since Virtuoso is used for digital back end design and analog circuits design. I thought you plan to to mixed (VHDL-Spice) simulation under a cadence+Spectre envirnement. Btw, it would be a normal task If you are familiar with back end. Your task will consist in gathering the digital parts (a netlist generated by design compiler) and the layout out of the analog circuits.

 

[jbeniston]

Typically you would import a post-layout Verilog netlist and DEF file. The Verilog netlist is used to create a schematic and the DEF the layout. You can then instantiate this as you would any other cell in your design.