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Cadence Design Systems, Inc. introduced C-to-Silicon Compiler, a high-level synthesis product supporting the creation and re-use of system-on-chip IP. The innovative technology in C-to-Silicon Compiler helps bridge the gap between register transfer level (RTL) models — commonly used to verify, implement, and integrate SoCs — and system-level models, usually written in C/C++ and SystemC.
C-to-Silicon Compiler is the first product delivered from a new initiative codenamed Sydney and was developed within an internal incubation group headed by Michael McNamara, vice president/general manager, C-To-Silicon Compiler. The product aims are twofold: to bridge the gap between the use of C as a design language and RTL description of the design, and to improve the silicon implementation of the design by providing a direct link between manufacturing constraints and the C description.
**broken link removed**articleID=209000061&cid=NL_edadl
Cadence Design Systems, Inc. introduced C-to-Silicon Compiler, a high-level synthesis product supporting the creation and re-use of system-on-chip IP. The innovative technology in C-to-Silicon Compiler helps bridge the gap between register transfer level (RTL) models — commonly used to verify, implement, and integrate SoCs — and system-level models, usually written in C/C++ and SystemC.
C-to-Silicon Compiler is the first product delivered from a new initiative codenamed Sydney and was developed within an internal incubation group headed by Michael McNamara, vice president/general manager, C-To-Silicon Compiler. The product aims are twofold: to bridge the gap between the use of C as a design language and RTL description of the design, and to improve the silicon implementation of the design by providing a direct link between manufacturing constraints and the C description.
**broken link removed**articleID=209000061&cid=NL_edadl