[SOLVED] Cadence Encounter - Synthesis faild due to Latch cell

[KHDAK]

Hi,

I am trying to synthesize a FPGA based design with Cadence RTL compiler to find out the performance difference with ASIC implementation. The elaboration phase works fine but when I try to synthesize "synthesize -to_mapped" I got an error message saying "unable to map design without a suitable latch". I am using COREX9GPHS_Nom.lib library for 130nm process. Can someone please explain what should I need to do.

Thanks

 

[rca]

I imagine the synthesis too indicate which latch made the issue, after that you need to read the RTL code to know what king of latch could implement the code, asynchronous set/reset, and if this kind of cell exist inside your liberty file.

 

[KHDAK]

I imagine the synthesis too indicate which latch made the issue, after that you need to read the RTL code to know what king of latch could implement the code, asynchronous set/reset, and if this kind of cell exist inside your liberty file.

Thanks rca,

It says "instance switch_reg[0] requires a simple latch : check the libraries for necessary latch cell, the cell could be marked unusable"

I think latch cells are not included in the library I am using "CORX9GPHS_Nom.lib".

 

[rca]

well the synthesis tool required at least a flop, a latch and basic logic gate like NAND, without these basic std cells the synthesis could not synthesis.

It is strange to have a library not compliant ?

Did you open the liberty file (basic editor is enought) to see how many cell there are and the different flop/latch available?

 

[KHDAK]

The error disappears after adding "lib_search_path" attribute. Thanks rca