Buffer insertion or cell upsizing

[goodhope]

How can I decide whether to insert a buffer or upsize the cell during delay optimization? Anyone knows the algorithms used in modern EDA tools?

 

[lailiya]

both buffer insertion and gate sizing can be used for delay optimization, i think most eda tools can try to resolve delay ploblem when under proper constrains using these two methods. you can google the two key works "buffer insertion" and "gate sizing" for more information. good luck!

 

[goodhope]

I know tools can do it. But I want the practical hand-on experience on doing buffer insertion and cell sizing. Or the algorithm inside EAD tools

 

[linuxluo]

hi,
maybe you can look up DAC conference paper. they can be found on internet.

 

[sandusty]

You can find DAC paper under
https://www.sigda.org/Archives/ProceedingArchives/Dac/

Actually, what you are going to deal with is the buffer number, size, and location....

 

[g3nster]

If you have STA results this would give you good indication whether to up size or down size cell. It all depends on delays on that path but you must take care that you do not cause skew conditions to other paths!