bonding pads_layout tips

[swathi.kamath]

Hi all

Can somebody please provide me some tips to layout bonding pads for CMOS layouts?

 

[raduga_in]

Please specify what kind of tips you would like to have ?

 

[swathi.kamath]

Hi Raduga

I would like to know the things that i need to consider while layin out the bondpads.. currently working with 90nm technology..Is there any detailed literature that you could provide?
That would be of great help.

 

[raduga_in]

Hi Swathi,

You can get preliminary doc about the pads and their layout at

**broken link removed**

Let me know if you need any more advanced info..

 

[swathi.kamath]

Hey Raduga


Thanx a lot for that url... that was quite useful.. ... there are a few questions in my mind... Right now i am migrating the bondpad from 180nm to 90nm technology... there are 3 layers that are used the purpose of which i am not really sure about..basically these are the 2 dummy DRClayers and PRbound layer... now the terminology might differ. But do u have any idea why these layers are used???
Also, would like to have more info related to bonding pads.

Warm regards
Swathi

 

[swathi.kamath]

Hi all


Please provide any info that u hav regarding bonding pads. Your help would be highly appreciated.


Warm regards
Swathi:|:|

 

[raduga_in]

Hey Swathi,

I really dono about the stuff in 90 nm technology ..
and also the references for the same
if you get please share with us ..

Thanks

 

[cmos_dude]

Hi Swathi
The Dummy layers are used to specify for the verification tool that the devices below are for a different rule set.
For example you must be using a thick gate layer on some of the devices, hence specifying for the tool that the devices below are different than the ones outside.
Now the purpose ooof the layers that you are talking abt might differ from process to process and also with foundries.

As for the prboundry layer, you might be using this layer to specify the boundry of your layout.
This layer will be later used for the LEF creation.

--Cmos_Dude