Basic Verilog inout query

[beowulf]

Hi,
I know this is very basic. I need inputs on how it can be resolved.

I am reusing a design which has a lot of inout ports

eg:
module existing_design (
inout [7:0] IO );
<LOGIC>
endmodule

Now I have to connect these inouts to my_design (top level wrapper) which has well defined input, output and inout ports
eg:

module my_design(
input[2:0] my_inputs,
output [2:0] my_outputs;
inout [1:0] my_io;

<LOGIC>

endmodule


Question:
How should I instantiate "existing_design" in "my_design"

Will this work..?


module my_design(
input[2:0] my_inputs,
output [2:0] my_outputs;
inout [1:0] my_io;

wire my_outputs;

wire [7:0] IO_wire;
assign my_outputs = IO_wire[5:3];
assign IO_wire[2:0] = my_inputs;

existing design i_existing (
.IO( my_io, //[7:6]
IO_wire[5:3], // outputs
IO_wire[2:0] // inputs
);
<LOGIC>

endmodule


Will the above work...?

Whats the best way to instantiate the existing_design in my_design

Thanks,
Beo

PS: Please ignore any syntax issues

 

[sam33r]

This will lead to glue logic in my opinion. Make sure there is no logic in your top module.

 

[lostinxlation]

in your example, the pin direction of IO doesn't match, because some are inputs, some are outputs and some are inout.
Separete them like,
.IO_in(my_inputs),
.Iut(my_outputs),
.IO_io(my_io),

And if my_io is bidirectional, you need to conrol the direction accordingly.