Basic Layout doubt about different delays in 3 parallel signals

[swaroopa]

I have 3 signals running in parallel ,Sig A,SIg B and Signal C. All the three are of equal width and length and spaced equally.
But i can find more delay in the signal B compared to Sig and Sig C.What is it due to?
Has it something to do with the capacitance???

Thanks.

 

[JesseKing]

Basic Layout doubt

I don't know this very exactly. Let me guess.

Maybe sig b is in the middle of the parallel wire group, so both a and can interfere b by crosstalk. Therefore, sig b have more delay than a and c. Change the drive strength of b twice than a and c might overcome this question.

 

[research235]

Basic Layout doubt

hello Swaroopa ..

wat ever jasseking had given is correct according to me . The cross talk effect is becoming more and more predominant in lower techlogy. I think prime time has a clear explanation of this effect and alos how to over come.. may be soem other tool might alos deal with this

suresh

 

[dkace]

Re: Basic Layout doubt

I agree that crosstalk may be the cause of the delay. But have you thought the possibility of paracitic capacitance or resistance in the Sig B line?
Is Sig B connected exactly the sam as A and C? Is it routing exactly the same as the other two?

If so, then crosstalk is the answer to this issue.

D.

 

[satyakumar]

Re: Basic Layout doubt

Hi,
I think the midle signal experiance more capacitance compared to other two signal, there is capacitance b/w sigA and sigB as well sigC and sigB. if we draw an equavalent ckt then the resulting parasitic capacitance effect is litle bit more on sigB. The cross talk comes when there is capacitance or inductor effect, due to more capacitance the crosstalk is more.

 

[xstal]

Re: Basic Layout doubt

I agree with you guys, it is cross talk delay that is coming into picture. Try to interchange the position of the signals before increasing the drive strength of the victim.

 

[pratap_v]

Re: Basic Layout doubt

hi Swaroopa
u said there are three signals and the signal B is causing more delay than others.
This can happen if sigA and SigC direcion is opposite to sigB. This may lead to setup voilation in ur design for this path. U can increase the drive strength of signalB, but be careful if u r victimising other two nets. Surely this is a crosstalk issue which is more prominent with latest tech.

 

[crazy_man]

Re: Basic Layout doubt

Guess its due to crosstalk.

 

[anoop12]

Re: Basic Layout doubt

Its a crosstalk problem. This problem is avoided by inserting ground lines inbetween.

 

[xreaver]

Re: Basic Layout doubt

Yes true crosstalk issue...the coupling capacitance seen by sig B is more because it is in the middle of sig A and B.. The capacitance seen by B is coming from both A and C. The signals A and C are seeing coupling capacitance from only one signal and thats B. As mentioned earlier, it can be reduced by inserting VDD or GND lines for shielding the signals A - B - C....