solvall
Junior Member level 2
bit blast
I have a module as shown below,
in RTL
module ABC ( PTA, PTB);
input [3:0] PTA;
output PTB;
...
endmodule
after synthesis, netlist in Gate-level obtained from Synopsys Design Compiler
module ABC ( .PTA({PTA_3, PTA_2,PTA_1,PTA_0}) , PTB);
input PTA_3,PTA2,PTA_1,PTA_0;
output PTB;
....
endmodule
I don't like this type port " .PAT({PTA_3, PTA_2,PTA_1,PTA_0})"
How can I retain bused I/O ports in verilog netlist?
My Design compiler is ver 2005-09
I have a module as shown below,
in RTL
module ABC ( PTA, PTB);
input [3:0] PTA;
output PTB;
...
endmodule
after synthesis, netlist in Gate-level obtained from Synopsys Design Compiler
module ABC ( .PTA({PTA_3, PTA_2,PTA_1,PTA_0}) , PTB);
input PTA_3,PTA2,PTA_1,PTA_0;
output PTB;
....
endmodule
I don't like this type port " .PAT({PTA_3, PTA_2,PTA_1,PTA_0})"
How can I retain bused I/O ports in verilog netlist?
My Design compiler is ver 2005-09