Automatic Gated Clock

[ivlsi]

Hi All,

How the Automatic Gated Clock should be inserted into the flow? Should I prepare the RTL code in some way for the Automatic Clock Gating?

In what cases it doesn't worth inserting the Automatic Gated Clock?

How could the Automatic Clock Gating be managed?

Thanks!

 

[wwfeldman]

what is an Automatic Gated Clock
inserted into what flow?
etc

your questions have no context

 

[ivlsi]

I'm talking about the Automatic Gated Clock, which is inserted during the synthesis....

 

[ThisIsNotSam]

I'm talking about the Automatic Gated Clock, which is inserted during the synthesis....

you need to learn standard terminology, your questions are always cryptic otherwise. the term you are looking for is clock gating.

why is it automated? because it is easy to do so.
why is it not done by hand? because it leads to mistakes
is it always worth it? the tools know when it is not worth. they also let you configure the minimum number of flops to be gated together with a shared enable condition.

 

[ivlsi]

OK, besides the min number of flops, what other configurations could be done for the clock gating insertion by tools (e.g. synthesizer)?

 

[ThisIsNotSam]

you can select what cells to use for gating. some are latch based, some are complex cells, some are simple AND-like cells.

 

[ivlsi]

1) In what cases the clock gating should be done manually? I know BackEnd tools insert the clock gating on the outputs of the PLLs. Are there more cases where the gated clock should be inserted manually?
2) It's clear that gating a single flop doesn't have a sense. So, what's minimum flop numbers should be used for the clock gating with the shared enable? E.g. will have the sense to gate the clock of 5 flops? 10 flops? 20 flops? How to choose this threshold?
3) So, as for the clock gating, the following setup should be done:
- selection the gating cell
- selection a min number of flops to be gated
What else? How should I define the above parameters? what are commands (e.g. for Synopsys DC)