Assuming recursive instantiation. Modelsim

[jiraiya]

I am new to verilog.

I wrote this small code where i am calling the add function in counter program. I get the following error when i try to simulate it-

# Region: /tb/DUT/u1/u1/u1/u1/u1/u1/u1/u1/u1/u1/u1/u1/u1/u1/u1/u1/u1/u1/u1/u1/u1/u1
# ** Error: (vsim-3036) Instantiation depth of '/tb/DUT/u1/u1/u1/u1/u1/u1/u1/u1/u1/u1/u1/u1/u1/u1/u1/u1/u1/u1/u1/u1/u1' is 76. Assuming recursive instantiation.

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Code Verilog - [expand]
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add.v - 
module add (a,b,c);
    input a,b;
    output c
    assign c=a+b;
endmodule
 
counter.v -
module counter (a,b,c,d,e,f);
    input a,b,d,e;
    output c,f;
    
    add u1 (a,b,c);
    add u2 (d,e,f);
endmodule
 
counter_tb.v-
module tb;
    reg a,b,d,e;    
    wire c,f;   
 
    counter DUT (a,b,c,d,e,f);
 
    initial 
    begin
      #0 a=1;b=1;
      #5 d=0;e=1;
       
       
    #10 $finish;
    end
    
initial
    begin
      $monitor("Time = %g    a =%b,b=%b,c=%b,d=%b,e=%b,f=%b", $time, a,b,c,d,e,f);
    end
endmodule

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May I know the reason for this error?Thank you.

 

[suresh_]

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Code Verilog - [expand]
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module add (a,b,c);
    input a,b;
    output c
    assign c=a+b;
endmodule

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May I know the reason for this error?Thank you.

Without commenting on the logic, I see that there is no semicolon for output c. Otherwise, it's simulating.

 

[ads-ee]

As suresh_ pointed out the only error is the missing semicolon for output c.

Logic wise the module names do not match the functionality of the implementation, e.g.:
1. add.v does nothing more than assign c=a+b;, which due to the single bit width a, b, and c can only be 0 or 1 so it instead implements an XOR operation: assign c=a^b;.
2. counter.v does nothing more than perform a parallel XOR operation on two different pairs of bits (a^b) and (d^e), which isn't counting.

This obviously isn't the code that had the problem with recursive instantiation, so I'm assuming you posted this code because you thought that your underlying logic was the root cause of the problem and not your recursive code, which I suspect was an attempt to iteratively make a counter out of single bit adds.


I still don't get why they teach Verilog like this...micro module instances to build up logic that is much easier to write behaviorally.

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Code Verilog - [expand]
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reg [15:0] counter;
always @ (posedge clk) counter <= counter + 1;

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