JEOvergaard
Junior Member level 1
Dear everyone
I am currently in midst of designing an integrated switched capacitor converter. But I am having some difficulties assessing MOSFET parasitic capacitances. This both goes for a single NMOS but also CMOS inverters. I am using TSMC018 in Cadence Spectre, to anyone wondering.
I have some ideas on how to do it, but I am not sure, which one is the better. First for a single NMOS transistor I would do one of the following:
All in all the three methods show quite similar results, but I would like to learn, how I should and shouldn't be doing this parasitic extraction. For a CMOS inverter I'd suppose it differs if you bias it with a 0 V or 5 V voltage source. Even doing so for a single NMOS transistor makes the capacitance vary quite a bit.
Best regards Jacob.
I am currently in midst of designing an integrated switched capacitor converter. But I am having some difficulties assessing MOSFET parasitic capacitances. This both goes for a single NMOS but also CMOS inverters. I am using TSMC018 in Cadence Spectre, to anyone wondering.
I have some ideas on how to do it, but I am not sure, which one is the better. First for a single NMOS transistor I would do one of the following:
- DC bias operating point parameter cgg (supposingly the sum of all capacitive parasitics at the gate, biasing with 5 V since it will be driven with 5 V. The capacitance naturally varies with applied Vgs.
- AC analysis: Biasing the gate with a 1 - 100 H inductor at 5 V and then supplying a 1 A AC current source directly to the gate measuring the resulting magnitude and calculating the capacitance based on magnitude and frequency.
- Transient analysis: Biasing the gate with a 1 - 100 H inductor at 5 V. Then I supply a constant current of 1 A and calculate the slope with ViVA. Then i use: i = C * dv/dt to calculate C.
All in all the three methods show quite similar results, but I would like to learn, how I should and shouldn't be doing this parasitic extraction. For a CMOS inverter I'd suppose it differs if you bias it with a 0 V or 5 V voltage source. Even doing so for a single NMOS transistor makes the capacitance vary quite a bit.
Best regards Jacob.