Are you satisfied with design service/ASIC house's die size

[tomku]

Does everybody satisfied with design service/ASIC house's result on their chip size? I think design service/ASIC house always quote their customers with very conservative size. Does customer have any choice besides buying their own tools which is usaully millions of dollars? Is there any tool that can measure the design service/ASIC house's performance on the die size.

 

[seasonyangd]

It is a good question and I　want to know too.

Magma have explore feature to evaluate the size earlier. But still need much license!!

 

[zelda]

Re: Are you satisfied with design service/ASIC house's die s

I have found a sound need web site may somewhat similar what you are looking for.
The web site is www.apexdesn.com
They have so called "Empty Space Evaluator" which acutally give insight on the empty space
left in a design. They also have 30 trial license. I have already requested.

 

[burnout]

Re: Are you satisfied with design service/ASIC house's die s

Hay, thanks for the tip. We also not satisfied with our existing design service result. And I cannot argue with them since we dont have P&R tool. I may checkout Apex's design service since they have lined up with some well known design service house.

 

[tomku]

Re: Are you satisfied with design service/ASIC house's die s

I have checked them out too, the idea seems very neat. Now I can verify my design service company's performance. I will find out how much our company have wasted during last two projects.
Then, I will tell my boss to reconsider the design service house. After all, even I not president of
the company. I still own some shares of the stock. Why not make our product more competive to others by making smaller die. I think people should make this tool as a verification tool like a sign-off for die-size
quality.

 

[moorhuhn]

Re: Are you satisfied with design service/ASIC house's die s

Well, you get the size of your chip AFTER you do the layout. So the quotation is always based on the estimation and therefore must be conservative, otherwise the design house will bankrupt. If you want to have control over the chip size, yield and chip production costs, you have to do more than just to give your RTL or netlist away. But to be able to do more means also to accept more risk and more initial costs.

 

[burnout]

Re: Are you satisfied with design service/ASIC house's die s

The reason that I am interested to find out the empty space in a chip is that our chip has very low utilization. The backend company said that it is only way to make chip routable and I have to believe them because we are not P&R expert. I just want to see whether there is way to double check their claim.

 

[zelda]

Re: Are you satisfied with design service/ASIC house's die s

I have got the program from Apex and ran on my design (taped out). The program is simple and easy to use. It is reporting 20% space can be reduced. Holly !!, if this is true. It really worth while for our company to look into the detail.

 

[CatKing]

Re: Are you satisfied with design service/ASIC house's die s

The reason that I am interested to find out the empty space in a chip is that our chip has very low utilization. The backend company said that it is only way to make chip routable and I have to believe them because we are not P&R expert. I just want to see whether there is way to double check their claim.

in the case of low metal layer used(2-4 Layer), and the scale is large(gatecount > 300K), the chip utilization will be as low as 50 %, otherwise the routebility will not be reached.
another issue is pad limit, if you have too much pads in your design which uses all of them around your chip, the core size will be large than your really core area in your design, but you have to accept it. for example, you have 400 pads, the width of each of them is 50um, and place them into square shaped chip, so each side of core area will be 100*50 = 5000um, but your core design maybe 3000*3000um, so the real core utilization must be (3000*3000)/(5000*5000) = 36% or less.

 

[burnout]

Re: Are you satisfied with design service/ASIC house's die s

Our chip is has 7 layers of metal and is not pad limited. We need to reserve top 2 layer for power (very dense). Effectively we only have 5 layers to route. We are suspecious that the chip we got is too big.
After running Apex's tool, we can visually see a lot of usable spaces. For the next project, we will ask service company to give us the placement before routing and verfication so that we can verify the floorplan.