Are UDP's & Task's in Verilog synthesizable ?

[kunal1514]

Hi All,

Can any body tell whether these UDP's & Task's in verilog are synthesizable or not if not why?

 

[sree205]

Synthesis

Tasks are not synthesizable coz its possible to specify delay in them.

 

[yasser_shoukry]

Re: Synthesis

I hope this article would help you, it is a part of Verilog Coding Styles pdfs

 

[Hards]

Re: Synthesis

Hi
Task are somtimes not synthesizable because in task we are defining delay. I think UDP is also not synthesisable

 

[vinod_g]

Re: Synthesis

if within task any delays r included then it will not synthesize

 

[raju3295]

Re: Synthesis

hi
i think
UDPs are synthesizable and the synthesis tool will do this by using mux

and i dont think tsks are synthesiable

 

[VLSI Banker]

Re: Synthesis

I've tried synthesizing UDPs using RC but they are not synthesizable

 

[raju3295]

Re: Synthesis

hi banker
i hv saw many RTL scripts and many were containing UDPs as thier leaf cell
am not able think a UDP which is not synthesizable since any UDP can be implemnted with muxes

 

[hgz]

Synthesis

You'd better not use them.

 

[sumit_techkgp]

Synthesis

Tasks and udp are meant for modelling and not at all synthesizable.
Sumit