Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Architectural issues in ASIC processor design

Status
Not open for further replies.

senmerida

Junior Member level 3
Joined
Oct 15, 2011
Messages
25
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Location
Bangalore
Activity points
1,438
What are the Architectural issues in FPGA and ASIC processor design and what are the factors affecting timing and performance of ASIC processors?
 

my question is general., whether its an architectural design or an RTL design.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top