Application Engineer in Bangalore

[entropy]

Job Description and Requirements The Synthesis and Formal verification specialist plays a critical role in the success of Synopsys’ customers as they design ASICs which push the limits of complexity, time to market and silicon technology. By enabling adoption of Synopsys' Synthesis and Formal verification design products and leading-edge methodologies ("flows"), he/she will bring in tangible and lasting improvements in performance, cost, quality, and development time for these ASICs. He/She work to solve complex technical challenges in the area of high frequency designs, deep sub-micron technology and low power. India Synthesis and Formal Verification expert’s today work on cutting edge 32nm and 28nm designs in the wireless, consumer and processor space. The designs that he/she work on range from a few million gates to several tens of millions of gates. He/She have the opportunity to work on to different design styles, methodology, different application domains and different complexity and process geometry nodes.



He/She will be expected to take advantage of opportunities provided to improve technical and job related skills; such as developing additional product breadth and leadership skills.



Requisition Requirements:



BE/BTech/MSEE (or equivalent) required with 2-5 years design experience. Deep understanding of design methodologies is required, with emphasis placed on the synthesis and formal verification. Knowledge of the back-end design process or experience with place and route , extraction, and LVS/DRC are a plus. Synopsys tool experience is desired, but not required. Excellent verbal, written and communication skills are required. Customer sensitivity, the ability to multiplex many issues & set priorities and the desire to exploit new technologies are essential for success in the position.



Location: Bangalore


Please drop your resume to noagain#hotmail.com. Enquiries are welcome.

Thanks!!

 

[sharif.shiek]

Hi,

I am Shareef Shiek B.tech (2011,ECE), looking for job in VLSI physical design even I have undergone PG DIPLOMA training to seek a challenging career and growth oriented position in the field of ASIC design and to work on challenging projects.I have strong knowledge on advanced digital design,CMOS Fundamentals, SoC Fundamentals, Floorplanning, Placement, Clock Tree Synthesis, Routing, Optimization, Parasitic Extraction, Static Timing Analysis, Physical Verification, Chip finishing. verilog HDL, C language, Cshell, TCL, PERL and I have done projects based on verilog HDL using XILINX ISE 9.2i simulator and RISC full chip with instance count of 60K and 15 macros at 90 nm technology using IC COMPILER.

Engineering Degree: B.Tech (Electronics and Communication Engineering)
Name of University: Jawaharlal Nehru technological University, Hyderabad
GPA Scores: 70%
Current Co: fresher with 6 months training experience in VLSI Physical Design
CTC Details: 0.0 lac
Notice Period: One week
Email : sharif.shiek@gmail.com


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Thanks & Regards..

Shareef Shiek..