Any recommended topology for comparator with 25MHz bandwidth, 120V/V gain, <4uA@1.2V current consumption in 65nm?

[melkord]

Any recommended topology for comparator with 25MHz bandwidth, 120V/V gain, <4uA@1.2V current consumption?
65nm technology.

 

[D.A.(Tony)Stewart]

The 25 MHz * 4uA * 100 dB gain is impossible to achieve at present due to tradeoff for RdsOn*Coss product into a 30pF load. Internal dynamic current of CMOS increases with f will grossly exceed Iq. Maybe in future with SiC or better. What do you want to compromise? BW Iq or Av? What source impedance, voltage, load and input/output dV/dt are you trying to compare ? Is the real question.

 

[KlausST]

Hi,

Why 100 dB?
My calculation says 42 dB.

Klaus

 

[D.A.(Tony)Stewart]

Hi,

Why 100 dB?
My calculation says 42 dB.

Klaus

Brainfart, makes no difference. He might consider a simple buffered inverter logic gate if he can live with the threshold tolerances.

 

[melkord]

The 25 MHz * 4uA * 100 dB gain is impossible to achieve at present due to tradeoff for RdsOn*Coss product into a 30pF load. Internal dynamic current of CMOS increases with f will grossly exceed Iq. Maybe in future with SiC or better. What do you want to compromise? BW Iq or Av? What source impedance, voltage, load and input/output dV/dt are you trying to compare ? Is the real question.

Hi,
Maybe I reduce Av to 80-100 V/V or BW to 20MHz. But Av is the first I want to sacrifice. Current consumption may can be increased to 5 uA.
The input is the output of an CSA or I/V Amp. So the output impedance of this amplifier can be considered low, but I do not know exactly how low yet. The same for its slew rate, but if I calculate the slope roughly, it would be like 2-5 V/us.

Btw, is there any reference that I can look out for predicting whether the specification if possible or not?

Hi,

Why 100 dB?
My calculation says 42 dB.

Klaus

Hi, is there any reference how to make this prediction?

 

[KlausST]

Hi,

120V/V gain,

A_dB = 20 x log(gain_V)
... = 20 x log(120)
... = 20 x 2.079
... = 41.58 dB
rounded up to 42 dB

Decibel - Wikipedia

en.wikipedia.org

dB calculate - decibel calculation dB calculator voltage power ratio sound pressure level matching dBA SPL sound pressure intensity ratios converter thd percent % audio engineering impedance matching bridging - sengpielaudio Sengpiel Berlin

dB calculate dB calculator decibel calculator voltage power ratio reference voltage power level matching dBA dB SPL sound pressure intensity ratios converter thd percent % audio engineering impedance matching bridging - Eberhard Sengpiel sengpielaudio.com

www.sengpielaudio.com

and many million others:
https://www.google.com/search?client=firefox-b-d&q=db+calculation (190 million hits)
https://www.google.com/search?q=online+db+calculator (28 million hits)

Did you do some little effort to find out on your own?

Klaus

 

[melkord]

Hi,


A_dB = 20 x log(gain_V)
... = 20 x log(120)
... = 20 x 2.079
... = 41.58 dB
rounded up to 42 dB

Decibel - Wikipedia

en.wikipedia.org

dB calculate - decibel calculation dB calculator voltage power ratio sound pressure level matching dBA SPL sound pressure intensity ratios converter thd percent % audio engineering impedance matching bridging - sengpielaudio Sengpiel Berlin

dB calculate dB calculator decibel calculator voltage power ratio reference voltage power level matching dBA dB SPL sound pressure intensity ratios converter thd percent % audio engineering impedance matching bridging - Eberhard Sengpiel sengpielaudio.com

www.sengpielaudio.com

and many million others:
https://www.google.com/search?client=firefox-b-d&q=db+calculation (190 million hits)
https://www.google.com/search?q=online+db+calculator (28 million hits)

Did you do some little effort to find out on your own?

Klaus

relax...I am asking about how I can make the prediction if the spec is possible...I am NOT asking about the conversion.

 

[KlausST]

Hi,

No need to relax. I am relaxed.

Your question clearly referred to the conversion. And you asked about a reference.
And I provided the answer as best as I can:
* Mathematically
* With a reference to the according Wikipedia page
* With a reference to online calculators

Klaus

 

[D.A.(Tony)Stewart]

The link I gave indicated 24GHz/mW was about optimal GBW for an LNA with gains from 15 to 23 dB and lithography from 23 n to 150n but you want a comparator with some noise figure and BER , so there are more variables that are TBD. Si technology is pretty mature now , but GaN FETs targeted for high power have 2 decades theoretically faster aren't mature yet.

 

[AMS012]

Any recommended topology for comparator with 25MHz bandwidth, 120V/V gain, <4uA@1.2V current consumption?
65nm technology.

You want to build a single comparator to slice the incoming waveform, with the above spec.? This is looking very much possible to me. You can try with what is called strong-arm latch. I am sure if you switch it at 25MHz, you will not consume more than 5uA.

 

[D.A.(Tony)Stewart]

You want to build a single comparator to slice the incoming waveform, with the above spec.? This is looking very much possible to me. You can try with what is called strong-arm latch. I am sure if you switch it at 25MHz, you will not consume more than 5uA.

Interesting old topology somewhat like the Astable full bridge flip flop, where dynamic power depends greatly on load capacitance f and Vdd but with zero static power.