Analog Layout showing incomplete nets though LVS matches

[Deepon]

Following the https://www.edaboard.com/threads/205992/ thread, I have done some advances. Now here is an odd problem I am facing with Cadence IC5141.

I have done a layout of the simple voltage divider circuit using the RNNPO_RF model file in UMC018 library.



Now, It was showing incomplete nets:



It shows that The out & gnd are incomplete nets, i.e not connected:



But after that I ran DRC & LVS. Both showed no errors & LVS Matched:







I don't know what is causing the problem. I have connected them with metal1 & gave proper connection to gnd with P_Diff.

 

[dgnani]

I am not sure how you get the incomplete net check w/o LVS, if this is a Layout-XL function then it depends on techfile rules, which are usually unreliable/incomplete/buggy