analog design flow question

[amireghlimi]

analog design flow

Hi

I am an ASIC designer who is getting to know analog,

Can anyone shed some light as to what is the usual
design flow in analog design, possibly with suggestions
on any share ware or free ware tools if applicable


Regards

 

[Fom]

If you say about design flow there shoud be serious tools. No shareware or freeware tools can provide complete design flow

 

[amireghlimi]

Hi Fom,

I hope you can tell me even if a partial answer, what is a normal
flow (with a bit of detail) and also even of not a full flow free/shareware
tool set, but a partial list will be nice too

Regards

 

[lxb97409]

As to the analog ICdesign,it's design flow can be follows":
1.determine what kind of circuit sturcture you are going to use.
2.optimize the circuit and simulation
3.layout and simulation

 

[uncle_urfi]

**broken link removed**

 

[guamak_menanak]

hope this can help amireghlimi or someone else!

 

[mitgrace]

I think you an study a good Book :
" Design of Analog CMOS Integrated Circuit"

Razavi

 

[amireghlimi]

Hi all,

Could anyone elaborate as to what are the usually extracted entites
in physical cycle and then used in simulation for verification ?

Regards

 

[rfic]

I think it is a good book: Analysis and Design of Analog Integrated Circuits

 

[rfic]

It is :

 

[duncan94022]

amireghlimi, the normal extracted parasitics are the interlayer and net capacitances. These are backannotated (ie written back to) the schematic for resimulation. You can also extract parasitic resistances, inductances, and mutual inductances. In the latter case it is called rclk extraction. As frequencies increase and device geometries get smaller, the inductance effects get more important.